The Piezoelectric Fix: How a UC San Diego Chip Achieves 96.2% Efficiency Converting Power for AI Data Centers

Between rows of GPU accelerators inside a modern AI data center sits a small, unglamorous component that hardly anyone writes about: the step-down DC-DC converter that turns the 48 volts on the rack bus into the low voltage the chips actually consume. That component has been quietly running out of headroom for years. In April 2026, engineers at the University of California, San Diego reported a prototype converter that stepped 48 volts down to 4.8 volts at a peak efficiency of 96.2% while delivering roughly four times the output current of earlier piezoelectric designs. The work, published in Nature Communications, matters less because it breaks a single benchmark than because it points a way past a physical limit the power-electronics industry has been talking itself around for half a decade.

Why the 48V-to-sub-volt step is the choke point

AI accelerators want enormous amounts of current at low voltage. Hyperscale racks distribute power at 48 volts to cut copper losses in the busbars, and the processors downstream are designed to run somewhere between about 1 and 5 volts depending on the workload. The DC-DC converter that lives between those two domains is not an afterthought — it is the component that decides how much of the electricity the utility sends actually shows up at the transistor, and how much escapes as heat along the way.

Data center electricity demand is growing quickly, with AI the dominant driver of that growth. At hyperscale, every percentage point of conversion efficiency translates directly into wasted power, extra cooling load, and higher operating cost. The inductive converters most of the industry has standardised on have been inching efficiency upward for a long time and are now running up against physical limits that do not bend to incremental improvement.

The step-down converter is also doing more work every generation. Modern AI accelerators are the most power-dense processors ever shipped in volume; a single rack of them can draw more than a small office building. The distribution bus voltage has already moved up from the 12V rails that dominated classic server designs to 48V precisely to keep that current manageable. The final step, from 48V down to the volt or less the silicon actually runs on, is where the losses now concentrate — and where architectural change pays off most directly.

That is exactly what Patrick Mercier, the UC San Diego electrical engineering professor who led the new work, said to his own institution's news office when the paper was announced: "We've gotten so good at designing inductive converters that there's not really much room left to improve them."

What was actually built

The UC San Diego team's approach, described in the Nature Communications paper, replaces the inductor's role with a piezoelectric resonator — a small component that stores and transfers energy through mechanical vibration rather than through a magnetic field. The resonator does not work alone. It is paired with commercially available capacitors in what the UC San Diego press release describes as a new configuration, creating multiple pathways for energy flow and reducing losses during conversion.

In lab measurements, the prototype stepped 48 volts down to 4.8 volts at a peak efficiency of 96.2%, and delivered roughly four times the output current of earlier piezoelectric-based step-down converters, per the same press release. The research was funded through the National Science Foundation's Power Management Integration Center, an Industry-University Cooperative Research Center, under NSF Award #2052809, with first authorship credited to electrical and computer engineering Ph.D. student Jae-Young Ko.

That combination — a large voltage ratio with relatively high current delivered at a high-90s efficiency — is specifically what earlier piezoelectric designs struggled to produce together. Pairing the resonator with capacitors does the unglamorous but important work of easing the strain on the piezoelectric element while giving current multiple routes to the output. The result is a topology, not a new material, which is part of why the team could build it with components available off-the-shelf.

It is also worth noting what this design does not try to do. It is not being advanced as a record against the very best inductive converters shipping today; it is being advanced as a path around the physical ceiling those devices are approaching, using a fundamentally different energy-transfer mechanism. That distinction matters for how the result should be read — as a demonstration of method, not a product-level benchmark.

Why the inductor keeps losing ground

Inductors are magnetic components, and magnetics are unforgiving. The more voltage you push across an inductor and the faster you switch it, the more heat and copper loss you generate, and the harder it becomes to shrink the part without giving up performance. Decades of accumulated circuit-design know-how have delivered genuinely excellent inductive converters, which is precisely why the discipline is now hitting diminishing returns. Further gains tend to require more exotic materials, tighter packaging, or more elaborate switching schemes.

Piezoelectric energy transfer avoids the magnetic field altogether. The resonator vibrates; those vibrations move energy; the supporting circuitry converts that motion back into usable electrical output. Interesting Engineering's summary of the work notes that piezoelectric components can in principle be shrunk more aggressively than equivalent inductors and are more compatible with semiconductor-style manufacturing, because they have no magnetic core to wind or to saturate.

The reason piezoelectric converters had not already displaced inductor-based designs in the places that need them most — high-current, large-ratio step-down — is that earlier attempts traded away exactly the properties AI infrastructure demands. They tended to perform well at smaller voltage gaps or at modest currents, but fell off when asked to do both at once. Solving that without reintroducing a magnetic component was the research target of the UCSD team's work.

There is a second motivation behind the push beyond inductors that tends to get less airtime: integration. Inductors are notoriously hard to embed into standard semiconductor packages. They want volume, they want clean magnetic paths, and they resist being printed or deposited alongside ordinary CMOS. Piezoelectric resonators, by contrast, are fabricated in ways that sit closer to the rest of the silicon supply chain, which is why the long-term case for them is not only about efficiency but about how close the power converter can physically move to the load it is supplying. The closer the conversion is to the chip, the smaller the conductor losses that are wasting modern rack designs.

The hybrid move: resonator plus capacitor

The paper's structural move is to accept that the resonator alone should not do all of the work. By arranging commercially available capacitors around the piezoelectric element in a configuration that creates multiple power-flow pathways, the design offloads part of the energy-shuttling duty onto components that are good at it and cheap to produce. That reduces the mechanical stress on the resonator during operation, and it also means the current capacity of the converter is no longer rate-limited by a single part.

ScienceDaily's coverage frames this as a deliberate architectural choice: rather than chasing a bigger or more exotic piezoelectric element, the team reached for a hybrid that pulls the best of two different component families into one circuit. That is the same philosophical move that took GaN and SiC power transistors from lab curiosity to mainstream data-center silicon over the past several years — incremental topology work on top of otherwise ordinary parts.

The practical consequence is that the UCSD design is not a one-off that requires a bespoke foundry. The authors built the prototype from components that already exist on distributor catalogs, paired through a new circuit design. That matters for whether a result like this ever leaves the lab. Approaches that depend on uniquely fabricated components tend to struggle to cross into production even when their benchmark numbers look better on paper.

What the numbers do — and do not — say

A 96.2% peak efficiency at roughly a ten-to-one step-down ratio is a headline number, and the fourfold current improvement over previous piezoelectric designs is exactly the kind of result that unlocks new applications. Taken together, they describe a prototype that is credible as a replacement target for the current generation of inductive converters in the specific role that matters most for AI — stepping 48V on the rack down to the sub-5V rails the accelerators actually consume.

What the numbers do not say is equally important. The reported figure is a peak efficiency, not an average across a full load profile, and peak numbers are routinely degraded by real-world duty cycles, aging effects, and thermal interactions inside a packed rack. The fourfold current improvement is measured against prior piezoelectric designs, not against the best current inductive converters — which remain the technology shipping in hyperscale data centers today. And nothing in the public coverage identifies the operating frequency, package size, or sustained power envelope of the prototype, any of which could constrain its path to a product.

None of that diminishes the result. It does mean the right way to read it is as a piece of evidence in favour of piezoelectric hybrids crossing a threshold that older piezoelectric topologies could not — not as an announcement that the inductor is about to disappear from the data center.

What could go wrong

Four distinct obstacles stand between the UCSD prototype and anything a hyperscaler would deploy in production.

The attachment problem. The UC San Diego press release is explicit that piezoelectric resonators physically vibrate as they operate, and that vibration means the parts cannot simply be soldered onto circuit boards using standard techniques without risking damage or performance loss. Data centers deploy boards by the million, and any component that needs a bespoke attachment process adds cost and yield risk. Solving packaging at scale is a programme of its own, not a footnote.

Thermal and reliability behaviour at sustained load. Peak efficiency on a test bench and average efficiency on a rack running continuously under varying loads are different properties. Inductor-based designs have decades of field data showing how they age, drift, and fail. A piezoelectric design has none of that, and how the mechanical element behaves under sustained stress over the multi-year service life of a server is an open question that this paper does not — and cannot yet — answer.

Competition from other non-inductor alternatives. Wide-bandgap semiconductors (GaN and SiC), multi-phase inductor topologies with more sophisticated controllers, and vertical power delivery architectures where the converter sits directly under the processor die are all active research and product areas. Each of them is also trying to claim the same 48V-to-sub-volt territory. A piezoelectric hybrid has to beat all of those, not just the older inductor it was benchmarked against.

Qualification and second-sourcing. Components that ship inside hyperscale server infrastructure go through qualification cycles measured in years, not quarters. Customers want evidence of stable performance across temperature, humidity, and vibration, plus supplier qualification and second-source availability. A prototype from a university lab, however elegant, is at the start of that journey, not near the end.

Each of these is solvable. None of them is solved.

What to watch next

Three milestones would meaningfully change how this technology should be read over the next eighteen months.

First, longer-term reliability data from the same or a closely related prototype — ideally including sustained-load testing, thermal cycling, and measurement of efficiency drift over time. Peak numbers are easy; durable numbers are what decide deployment.

Second, packaging and integration progress that addresses the attachment and handling constraints called out in the announcement. If the team can show a manufacturable path to get these parts onto standard boards, the product case sharpens quickly; if not, the design stays a lab demonstration for longer.

Third, an industry partnership signal. Power-electronics research of this kind rarely scales through university work alone. A collaboration with a merchant power-IC supplier, a hyperscaler's silicon team, or a specialist power-module vendor would be the most concrete indicator that the result is being taken seriously as a product pathway, rather than only as a paper.

Mercier himself was careful to temper the finding. Piezoelectric-based converters, he said in the study announcement distributed via EurekAlert, "aren't quite ready to replace existing power converter technologies yet." In the same announcement he argued that the approach has a lot of room to grow and the potential to outperform anything that has come before — a trajectory, not an arrival. That framing is the right way to read this result. The value of a paper like this sits less in the specific percentage than in the direction it implies.

Key takeaways

• Engineers at UC San Diego's Jacobs School of Engineering reported a hybrid DC-DC step-down converter that stepped 48 volts down to 4.8 volts at a peak efficiency of 96.2%, published in Nature Communications in April 2026.
• The prototype delivered roughly four times more output current than earlier piezoelectric-based designs, solving the voltage-ratio-and-current problem that has historically kept piezoelectric converters out of high-power applications.
• The design replaces the inductor's magnetic energy transfer with a piezoelectric resonator paired with commercial capacitors, creating multiple power-flow pathways that ease the load on the resonator.
• The work was funded through the NSF Power Management Integration Center under Award #2052809, with Ph.D. student Jae-Young Ko as first author and Professor Patrick Mercier as senior author.
• The technology is prototype-stage; component-attachment limits, sustained-load reliability, qualification cycles, and competition from other non-magnetic approaches are the most significant obstacles between the benchmark and deployment.
• The immediate significance is not that the inductor is obsolete, but that piezoelectric hybrids have shown, for the first time, the right combination of efficiency and current at the ten-to-one step-down ratio the AI data center actually needs.